A Malleable Architecture Generator for FPGA Computing

The Malleable Architecture Generator (MARGE) is a tool set that translates high-level parallel C to connguration bit streams for eld-programmable logic based computing systems. MARGE creates an application-speciic instruction set and generates the custom hardware components required to perform exactly those computations speciied by the C program. In contrast to traditional xed-instruction processors, MARGE's dynamic instruction set creation provides for eecient use of hardware resources. MARGE processes intermediate code in which each operation is annotated by the bit lengths of the operands. Each basic block (sequence of straight line code) is mapped into a single custom instruction which contains all the operations and logic inherent in the block. A synthesis phase maps the operations comprising the instructions into register transfer level structural components and control logic which have been optimized to exploit functional parallelism and function unit reuse. As a nal stage, commercial technology-speciic tools are used to generate connguration bit streams for the desired target hardware. Technology-speciic pre-placed, pre-routed macro blocks are utilized to implement as much of the hardware as possible. Marge currently supports the Xilinx-based Splash-2 reconngurable accelerator and National Semi-conductor's CLAy-based parallel accelerator, NAPA. The MARGE approach has been demonstrated on systolic applications such as DNA sequence comparison.